Timing Exceptions

Timing Exceptions 

Timing exceptions are nothing but constraints which don’t follow the default when doing timing analysis. The different kinds of timing exceptions are

1. False path: If any path does not affect the output and does not contribute to the delay of the circuit then that path is called false path. Examples for paths are shown below.

a) Asynchronous paths

b) static paths

c) Non-functional paths

2. Multi-cycle Path : Multicycle paths in a design are the paths that require more than one clock cycle. Therefore they require special Multicycle setup and hold-time calculations

3. Min/Max Path : This path must match a delay constraint that matches a specific value. It is not an integer like the multicycle path. For example:Delay from one point to another max: 1.67ns; min: 1.87ns

4. Disabled Timing Arcs : The input to the output arc in a gate is disabled.
 For e.g. 3 input and gate (a, b, c) and output (out). If you want you can disable the path from input ‘a’ to output ‘out’ using disable timing arc constraint.

Different paths:

False path:

·      Not a valid path for TIMING (setup and hold across different clock domains)

·      Need not worry to meet setup and hold constraints for this path

E.g.:  (i) All asynchronous paths

            (ii) static paths (Timing for RESET pin)

            (iii) Non-functional paths

Static path:

Non-functional path:

­Multi Cycle paths:

False paths basics and examples