Clocks

set_clock_uncertainty -setup 0.2 [get_clocks  SYSCLK]

set_clock_uncertainty -hold 0.05 [get_clocks  SYSCLK]

For setup, uncertainty means the effective clock period is reduced by that amount.

For Hold, uncertainty is the extra timing margin that need to be satisfied

What are the components of clock uncertainty:

-        Clock jitter, any pessimism, PLL uncertainty

-        Generally, we take 10-15% of clock period

-        Will make it zero/reduce while sign-off

Inter clock uncertainty:

set_clock_uncertainity  -from  VIRTUAL_CLK   -to   SYS_CLK  -setup  0.2

set_clock_uncertainity  -from  VIRTUAL_CLK   -to   SYS_CLK  -hold   0.05

Clock Latency:

Total clock latency = Insertion delay + network delay

Source delay (insertion delay):

-        Delay from clock source (PLL) to the clock definition point.

Network delay:

-        Delay from Clock definition point to the CK pin (clock pin of the FF)

set_clock_latency 1.8 -rise [get_clocks MAIN_CLK]

set_clock_latency 1.8 -fall [get_clocks MAIN_CLK]

set_clock_latency   0.8 [get_clocks MAIN_CLK]                          # Specifying only network latency

set_clock_latency   0.8 [get_clocks MAIN_CLK]  -source            #specifying only source latency

Important difference b/w source and n/w latency:

-        Once CTS is built (Post CTS), n/w delay can be ignored

o   Assuming set_propogated_clocks for this clock is defined. So, PT calculates the network delay. Use switch full_clock_expanded to report_timing command to see this delay.

o   But, source latency is there always even CTS is built and needs to be considered

-        So, Before CTS is built (PRE-CTS), network delay is an estimate of the delay of clock tree prior to CTS