Source synchronous Interface
1. Why there is trade-off b/w setup and hold violations?
2. What is the best way to fix CG setup and hold violations?
3. How skew affects setup and hold?
4. Why hold is checked at the low voltages also at FF?
5. What is ECO flow that you have worked on?
6. At SOC level,
7. Constraints development
8. Multi frequency clocks are valid?
- Yes. those are valid. Otherwise we need to put constraint as asynchronous in the constraints.
9. How PT takes care of multi freq violations?
- Finds common base period
10. Which domain have you worked in SoC level?
11. AMD is working on 7nm, GF?
1. Why there is trade-off b/w setup and hold violations?
2. What is the best way to fix CG setup and hold violations?
3. How skew affects setup and hold?
4. Why hold is checked at the low voltages also at FF?
5. What is ECO flow that you have worked on?
6. At SOC level,
7. Constraints development
8. Multi frequency clocks are valid?
- Yes. those are valid. Otherwise we need to put constraint as asynchronous in the constraints.
9. How PT takes care of multi freq violations?
- Finds common base period
10. Which domain have you worked in SoC level?
11. AMD is working on 7nm, GF?
No comments:
Post a Comment