Interview Queries

1. What are worst setup and hold corners? why?
2. Difference b/w CW and RCW corners? Which is the worst case out of these two?
3. What are the different checks we do during timing sign-off?
4. What is MPW?
5. What checks or happens of symmetric rise/fall cells are not there in data path?
6. What are your roles in qualcomm?
        - ECO fixing
                 Tweaker, PT ECO and manual
        - Setting Flat and hier runs
        -  constraints validation
        - Full flat runs
        - Automation in perl and tcl

7. ECO Fixing:
which tools do you use
what is the procedure

8. Why hier runs are needed and what is the diff b/w flat and hier?
9.Do you generate constraints?
10. What validation do you do for constraints?
11. What are pvt corners and voltages for setup and hold>
12. If SDF and netlists are given, what is procedure do you follow for HOLD free design at gate level?
13. What is the clock uncertainity for setup (60ps)?
14 .Freq - 1.4 GHz
15. Design - 2 million gates
16. Logic depth - 20 levels
17. What kind of ECOs you have given>
both block level as well as interface ECO
mainly setup and hold
DRC (min tran and max cap)
Leakage

18. Which vt ?
Mixed one
Mostly LVT (80%)
RVT (10%)
10% ULVT

19.