Min pulse width violation and fixing

http://tech.tdzire.com/what-is-minimum-pulse-width-check-and-pulse-absorption/

It is important for clock signal to ensure proper performance/functionality of sequential cells.

Definition:  
         This check ensures the width of clock should be more than min specified value.

Ensures that width of the clock signal is wide enough for the cell's internal operations to complete. i.e,.
It is min pulse width of the clock it has to maintain to get a stable output you need.

Impact:
       It can't capture at the edge of clock signal. So data may miss at that point.

Why does it shrink:
     Due to unequal rise and fall delays of combinational cells.

Detailed explanation:
Let us assume a clock entering a buffer. If the rise delay of that buffer is more than fall delay, the output clock will have less width than the input.

See the following figure which illustrates the same. So think of. what will happen to the same clock signal, when it passes through a series of same type of buffers. The width of the clock signal keeps decreasing, and at a point when the buffer delay is more than the clock pulse width, the clock pulse gets absorbed. This is known as Pulse absorption. So it is important to perform MPW check.

How to fix:
Keep symmetry rise and fall delays clock tree cells.

How to constrain in PT:

set  timing_enable_clock_constraints  true

#define min/max  pulse widths
set_pulse_clock_min_width
set_pulse_clock_max_width

#Remove/ignore MPW checks at particular sequential cells
remove_min_pulse_width

Query:
If asymmetric rise and fall delay cells present in the data path, what checks will be violated?
    - Data path delay means it is arrival time. If arrival time increases, setup violation comes otherwise hold violation comes.


From other website:

In ETS(or TEMPUS as the newest Cadence tool for STA is called), you will see a report like this:

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---------------------------------------------------------------------------------------------------------------                                     SEQUENTIAL CLOCK PULSE WIDTH    ---------------------------------------------------------------------------------------------------------------     Pin                                Required     Actual Pulse      Slack         Clock Name     View Name                                       Pulse Width      Width    ---------------------------------------------------------------------------------------------------------------    clk_ctrl_reg/CP (high)             0.3202          2.9731          2.6529       src_clk         func_min

In this example, the clock period is 6ns with a duty cycle of 50%.i.e. Here, the clock signal at clk_ctrl_reg/CP should be high at least for 0.3202ns (please note that the default time unit is ps in TEMPUS). The actual signal is high for 2.9731ns. Hence there is no minimum pulse width violation at the CP pin for src_clk.

Constraining the design
Now, let us see how you can specify this constraint for your design.

1. Using .lib file
Minimum pulse width depends on the technology node and the standard cell library design. You will have these modeled in your .lib file. Look for timing_type : min_pulse_width; in your liberty file. These will be defined for clock, reset and preset pins of a flop, or the enable pin of a latch.
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pin (CP) {       clock : true;       direction : input;       max_transition : 2.5;       capacitance : 0.00774191;       timing () {         related_pin : "CP";         timing_type : min_pulse_width;         rise_constraint (mpw_constraint) {           index_1 ("0.1, 0.6, 1.3, 1.9, 2.5");           values ("0.131, 0.800, 1.596, 2.392, 3.066");         }         fall_constraint (mpw_constraint) {           index_1 ("0.1, 0.6, 1.3, 1.9, 2.5");           values ( "0.361, 0.800, 1.596, 2.392, 3.066" );         }       }

The index_1 is the transition at pin CP, and the last value in the table is the max_transition of the pin. The values denote the minimum pulse width values for the pin transition specified.
2. SDC command ‘set_min_pulse_width’
To specifically set the minimum pulse width constraint, you can use the command set_min_pulse_width
1 2	set_min_pulse_width -high 3.0 [all_clocks] set_min_pulse_width -low  2.0 [all_clocks]

If neither high now low is specified the constraint applies to both high and low signal levels.

Reporting the violations
You can use in majority of STA tool, report_timing or a similar command.

1	report_timing -check_type pulse_width

You can also use the command report_min_pulse_widthin TEMPUS to report the pulse width values.