Problem:
To know how much fix is required to get rid of all violations; instead of putting actual cells on the path, delay is annotated as shown below and checks whether is it causing any issue anywhere.
When there are some buffers in between 2 pins and you want to bypass them by keeping some delay for analysis purpose in PT.
set_annotated_delay
-cell -load_delay 0.05
-from U1/U2/U3/A -to U1/U2/U3/Z
set_annotated_delay:
NAME
set_annotated_delay
Sets the net or cell delay value between two pins.
SYNTAX
string set_annotated_delay -cell | -net
[-rise]
[-fall]
[-min]
[-max]
[-load_delay load_delay_type]
[-from from_pins]
[-to to_pins]
[-of_objects objects]
[-cond sdf_expression]
[-increment]
[-delta_only]
[-worst]
-variation variation_object
delay_value
string load_delay_type
list from_pins
list to_pins
string sdf_expression
float delay_value
ARGUMENTS
-cell Specifies that the delay annotated is a cell delay. The -cell
and -net arguments are mutually exclusive; you must specify one,
but not both.
-net Specifies that the delay annotated is a net delay. The -net and
-cell arguments are mutually exclusive; you must specify one,
but not both.
-rise Indicates that the delay is for the data rise transition. If
you do not specify either -rise or -fall, both values are set.
-fall Indicates that the timing check is for the data fall transition.
If you do not specify either -rise or -fall, both values are
set.
-min Use this option only if the design is in min_max mode (min and
max operating conditions). Specifies the minimum delay for both
data rise and data fall transitions.
-max Use this option only if the design is in min_max mode (min and
max operating conditions). Specifies the maximum delay for both
data rise and data fall transitions.
-load_delay load_delay_type
Specifies whether load delay is to be included as part of anno-
tated net delays or as part of annotated cell delays. Allowed
values are net or cell. Load delay is the portion of cell delay
resulting from the capacitive load of the net the cell is driv-
ing. All timing arcs of the same net and of the same cell, must
be annotated with the same load_delay_type.
-from from_list
Specifies a list of leaf cell pins and top level ports that are
the startpoints of the timing arcs for which delays are anno-
tated. The -from/to and -of_objects arguments are mutually
exclusive; you must specify one, but not both.
-to to_list
Specifies a list of leaf cell pins and/or top level ports that
are the endpoints of the timing arcs for which delays are anno-
tated. The -from/to and -of_objects arguments are mutually
exclusive; you must specify one, but not both.
-of_objects objects_list
Specifies a list of timing arcs (created with the get_tim-
ing_arcs command) on which to annotate. The -of_objects and
-from/to arguments are mutually exclusive; you must specify one,
but not both.
-cond sdf_expression
Use this option only if the library has a condition attached to
the specified delay timing arc; otherwise, an error message is
generated. Specifies the condition for which the annotated
delay is valid. The syntax of the condition must match the con-
dition specified in the library using the construct sdf_cond.
The syntax is the same one used in the Standard Delay Format
(SDF).
-increment
Specifies that the delay is to be incremented to the current
delay of the specified timing arc. It should be noted that if
this command is used before a timing update, the current delay
could be 0.
-delta_only
Specifies that the annotated delay is to be added to the net
delay value calculated by PrimeTime. You cannot use this option
with -cell.
-worst This option is not yet implemented, so it is ignored.
delay_value
Specifies the delay value between pins on the same cell, in
units consistent with the technology library used during opti-
mization. For example, if the technology library specifies
delay values in nanoseconds, delay_value must be expressed in
nanoseconds.
-variation variation_object
Specify a variation to annotate on all arcs between the from and
to pins. The variation_object must be created using the cre-
ate_variation command.
DESCRIPTION
Annotates the cell delay between two or more pins on a cell, or the net
delay between two or more pins on the same net, in the current design.
With the -net option, pins in the from_list must be cell output or
inout pins, and pins in the to_list must be cell input or inout pins.
With the -cell option, both the -from and -to options are required.
Pins in the from_list must be cell input or inout pins, and pins in the
to_list must be cell output or inout pins. To verify that the back-
annotation done by set_annotated_delay is correct, run the update_tim-
ing command.
Load delay, also known as extra source gate delay, is the portion of
cell delay caused by the capacitive load of the driven net. Some delay
calculators consider load delay part of the net delay and others con-
sider it part of the cell delay. If your annotated delay value (for
either cell or net) assumes that load delay is part of the cell delay,
use -load_delay cell. If your delay value assumes that load delay is
included in the net delay, use -load_delay net. By default, load
delays are assumed to be in cell delays, so they appear in report_tim-
ing path listings.
The specified delay value overrides the internally-estimated cell and
net delay value. If the specified pins are not in the same cell or on
the same net, when the timing is updated an error message is generated
and delay_value is discarded for those pins.
If a timing arc has annotated delta delay (set_annotated_delay -net
-delta_only) and then total arc delay is annotated (set_annotated_delay
-net), the arc delay is assumed to include the delta. In other words,
delta delay is not used if delay is annotated. The annotated delta
delay becomes significant once the annotated delay is removed.
The set_annotated_delay command can be used for pins at lower levels of
the design hierarchy. Pins are specified in the format of
INSTANCE1/INSTANCE2/PIN_NAME.
To list annotated delay values, use the report_annotated_delay command.
To remove the annotated cell or net delay values from a design, use the
remove_annotated_delay or the reset_design command.
EXAMPLES
The following example annotates a cell delay of 20 units between input
pin A of cell instance U1/U2/U3 and output pin Z of the same cell
instance. The delay value of 20 includes the load delay.
pt_shell> set_annotated_delay -cell -load_delay cell 20 -from
U1/U2/U3/A -to U1/U2/U3/Z
The following example annotates a rise net delay of 1.4 units between
output pin U1/Z and input pin U2/A. The delay value for this net does
not include load delay.
pt_shell> set_annotated_delay -net -rise 1.4 -load_delay cell -from
U1/Z -to U2/A
The following example annotates a rise net delay of 12.3 units between
the same output pins. In this example, the net delay value includes
load delay.
pt_shell> set_annotated_delay -net -rise 12.3 -load_delay net -from
U1/Z -to U2/A
SEE ALSO
current_design (2), link (2), read_sdf (2), remove_annotated_delay (2),
report_annotated_delay (2), report_timing (2), reset_design (2).
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