Sentences

• Hypocracy:
• A situation in which someone pretends to believe something that they don't really believe, or that is the opposite of what they do or say at another time...

E.g.:

• Why can't politicians just be honest with themselves and stop all this hypocrisy?

a situation in which someone pretends to believe something that they do not really believe, or that is the opposite of what they do or say at another time

Static Timing Analysis basics:

STA:
No simulation; no inputs required
Puts worst timing to check timing violations based on paths; pessimistic approach
Fast, thorough

Dynamic Timing Analysis:
Apply vectors to inputs and check violations
Very accurate but very slow.

Different paths:
False paths
Multi Cycle paths
Latch timing borrow

Clocks:
Defining clocks; different ways
Generated clock
Latency: source + network
skew, jitter, uncertainity

OCV vs AOCV: In which corner case OCV derate is better compared to AOCV

setup and hold slack

Setup violations can be resolved by increasing clock path delay
Hold  violations can be resolved by increasing Data path delay

Fixing setup and hold violations are reverse in nature i.e., if setup can be fixed by adding 1 buffer in some path then hold can be fixed by removing buffer in that path.

You can live with setup violation(works with lesser frequency)  but not with hold violation. 

Max frequency of any circuit

Important equations:
       Clock period >= Setup time + Hold time
       Tclk,min > Tcq1+Tcomb+Tsu2
       Thold < Tcq,min + Tcomb,min

For any circuit, to find out max frequency of the circuit:
     Min clock period = max (F2F delay, Clock_to_out_delay, Pin_to_pin delay)

F2F dealy:         Find out all possible F2F delay and choose worst one out of them.
CK_to_OUT:    Find out all possible Clock to Output pin delays and choose worst one out of them.
pin_to_pin:       Find out all possible pin to pin delays and choose worst one out of them (i.e., in_to_out, or other combinational pin to pin delays in the circuit)

Few points on clock frequency:
          Individual FF characteristics Tsu, Th, Tcq are independent of clock frequency and only dependent on device sizes and technology.

Frequency affects path delays (can be critical paths) and setup & hold slacks but not individual cell delays.

check_timing: No Clock

1. When generated clock constraint is not defined

2.  Netlist issues
         - connectivity issues

3. case value on clock net is defined