STA:
No simulation; no inputs required
Puts worst timing to check timing violations based on paths; pessimistic approach
Fast, thorough
Dynamic Timing Analysis:
Apply vectors to inputs and check violations
Very accurate but very slow.
Different paths:
False paths
Multi Cycle paths
Latch timing borrow
Clocks:
Defining clocks; different ways
Generated clock
Latency: source + network
skew, jitter, uncertainity
No simulation; no inputs required
Puts worst timing to check timing violations based on paths; pessimistic approach
Fast, thorough
Dynamic Timing Analysis:
Apply vectors to inputs and check violations
Very accurate but very slow.
Different paths:
False paths
Multi Cycle paths
Latch timing borrow
Clocks:
Defining clocks; different ways
Generated clock
Latency: source + network
skew, jitter, uncertainity
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