1. What are different types of constraints and tell me with basic commands?
2. ECO - what the basic flow? Which order do you fix?
3. Scenario:
In the data path, there is max cap violation and setup violation trade-off i.e., once you fix max cap violation, setup violation is happening. How do you handle this scenario?
Ans: Fix max cap violation at that particular cell. Try to optimize data path (Upsizing/Changing vt/buffering) after that particular cell which implies optimization doesn't affect max cap violation at that particular cell.
4. In the given start point and end point; does fixing setup violation lead to hold violation?
Ans: YES.
5. For a given start and end point pairs, does setup and hold violations happen?
Ans: YES. There may be different paths from one start point to the same end point.
6. Noise
7. If there are violations from one block to another block. What is the best method do you guide PNR engineer to fix setup and hold violations for routing?
8. Do you have hands on experience with DC?
9. What is difference b/w OCV, AOCV, POCV and explain each?
10. Commands:
a) difference b/w set_input_delay and set_max_delay?
If i specify set_max_delay -to PIN; does it include/exclude/doesn't consider insertion delay?
b) What is the difference b/w below 2 commands and which is preferable
set_driving_cell, set_transition_time
11. What is multi cycle path and why do we define them
How do we specify them for setup and hold
If hold mcp is not mentioned, what happens?
Why should i check hold at zero cycle, if i check at prev edge, what happens?
12. What is MMMC?
why do we check at multi corners?
How do you handle multiple modes at constraints level?
13. setup corners
14. Hold corners:
- why do we check hold at low voltages?
15. What is the dependency of temperature on setup and hold times?
16. How setup time changes from SS_0.675_cw_m40, SS_0.675_cw_0c, SS_0.675_cw_125c?
17. How the setup and hold margins are defined for specific project?
18. CPPR and calculation with example?
2. ECO - what the basic flow? Which order do you fix?
3. Scenario:
In the data path, there is max cap violation and setup violation trade-off i.e., once you fix max cap violation, setup violation is happening. How do you handle this scenario?
Ans: Fix max cap violation at that particular cell. Try to optimize data path (Upsizing/Changing vt/buffering) after that particular cell which implies optimization doesn't affect max cap violation at that particular cell.
4. In the given start point and end point; does fixing setup violation lead to hold violation?
Ans: YES.
5. For a given start and end point pairs, does setup and hold violations happen?
Ans: YES. There may be different paths from one start point to the same end point.
6. Noise
7. If there are violations from one block to another block. What is the best method do you guide PNR engineer to fix setup and hold violations for routing?
8. Do you have hands on experience with DC?
9. What is difference b/w OCV, AOCV, POCV and explain each?
10. Commands:
a) difference b/w set_input_delay and set_max_delay?
If i specify set_max_delay -to PIN; does it include/exclude/doesn't consider insertion delay?
b) What is the difference b/w below 2 commands and which is preferable
set_driving_cell, set_transition_time
11. What is multi cycle path and why do we define them
How do we specify them for setup and hold
If hold mcp is not mentioned, what happens?
Why should i check hold at zero cycle, if i check at prev edge, what happens?
12. What is MMMC?
why do we check at multi corners?
How do you handle multiple modes at constraints level?
13. setup corners
14. Hold corners:
- why do we check hold at low voltages?
15. What is the dependency of temperature on setup and hold times?
16. How setup time changes from SS_0.675_cw_m40, SS_0.675_cw_0c, SS_0.675_cw_125c?
17. How the setup and hold margins are defined for specific project?
18. CPPR and calculation with example?
19. Let us assume you don't have chance to optimise data path cells. Then what is your approach to fix setup violations?
20. What is signal integrity?
Agressor and victim nets
how to fix
21. How do you sign-off design? What do you check? Do you use any specific tools?
20. What is signal integrity?
Agressor and victim nets
how to fix
21. How do you sign-off design? What do you check? Do you use any specific tools?
Thanks for sharing! Please continue writing more articles sir!
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