check_timing:
shows possible timing violations for design
Checks the assertions and structure of the design for potential timing violations.This command is used to identify possible problems before generating timing or constraint reports.
This command also prints which checks it performs. If a check reveals a violation, the command also prints a message about the violation. By default, the message contains a summary of the violation. To get more information about violations, use the -verbose option.
No clock:
Warns if no clocked signal reaches a data check register clock pin
In this case, no setup or hold checks are performed on the constrained pin.
How to check:
get_attribute [get_pins clock_pin_path] clocks
Possible reasons:
Not defining properly generated clocks
Netlist issues
Generated clocks:
Checks generated clock network
The master must be driven by a clock source.
There can't be loops of generated clocks. i.e., If CLK2 is generated from CLK1 then CLK1's source should not be CLK2.
multiple_clock
Warns if multiple clocks reach a register clock pin. If more
than one clock signal reaches a register clock pin, and tim-
ing_enable_multiple_clocks_per_reg is set to FALSE, then it is
undefined which one is used for analysis. In this case, use
set_case_analysis so only one clock can propagate from its
sources to the register clock pin. Using this check and the
no_clock check run significantly faster than other checks.
Hence, to save time, user may want to issue these checks sepa-
rately from other checks.
no_driving_cell
Warns if a port does not have any driving cell. This warning is
issued only when the net connected to the port has parasitics.
In such case, the accuracy of delay calculation could be
impacted, as a default strong driver is assumed in absence of
driving cell definition. Especially, in presence of crosstalk, a
port with no driving cell could act as a strong aggressor which
could lead to significant amount of pessimism in the analysis.
Also, a port with no driving cell could act as a string victim,
which could underestimate the crosstalk effect.
no_input_delay
Warns if no clock related delay specified on an input port,
where it propagates to a clocked latch or output port. With
-verbose, the port name will be listed. Note that with tim-
ing_input_port_default_clock set to 'true', a default clock will
be assumed for the input port. Otherwise it will not be clocked,
and the paths are unconstrained. In this case, if there is no
input delay specified, check_timing will not generate warnings.
partial_input_delay
Warns if any port has partially defined input delay. This hap-
pens when set_input_delay -min is applied on a port to set the
min input delay with respect to a clock, however no
set_input_delay -max is applied to that port to specify the max
delay, or vice versa. As a result, some paths starting from the
port with partially defined input delay may become unconstrained
and some potential violations could be missed.
unconstrained_endpoints
Warns about unconstrained timing endpoints. This warning identi-
fies timing endpoints (output ports and register data pins) that
are not constrained for maximum delay (setup) checks. If the
endpoint is a register data pin, it can be constrained by using
create_clock for the appropriate clock source. You can constrain
output ports using the set_output_delay or set_max_delay com-
mands.
unexpandable_clocks
Warns if there are sets of clocks for which periods are not
expandable with respect to each other. The checking is only done
for the related clock domains, such as ones where there is at
least one path from one clock domain to the other. This could be
because of an incorrectly defined clock period for one or more
of the clocks. Another possibility is when asynchronous clocks
with unexpandable periods are interacting where they should have
been defined in different clock domains.
unconnected_pg_pins
Checks that each power and ground pin is connected to a UPF sup-
ply net. The connection can be implicit (e.g., power domain) or
explicit (for example, connect_supply_net).
generic cells:
Warns about generic (unmapped) cells in the design.
Timing of paths through generic cells is inaccurate because these generic cells have zero delay.
ideal clocks:
Shows the clocks that are not defined as propogated clocks.
Generally, all clocks should be defined as propogated so that clock network timing is accurately calculated.
latency_override
Warns of clock latency specification conflicts. If clock source
latency is defined for both a clock and its port (source pin),
the source latency for clock object is ignored. If input_delay
is set on clock port, which also has source latency specified,
the input_delay is ignored as a source latency. Also warns if
more than one clock latency fan out to any latch clock pin.
loops Warns of combinational feedback loops. Combinational feedback
loops are not analyzed. If the feedback loop is not broken by
set_disable_timing, it is automatically broken by disabling one
or more timing arcs.
http://tech.tdzire.com/what-is-a-timing-loop/
EXAMPLES
The following example checks timing of the current design and shows
summary information of potential problems. The checks performed are
those defined by timing_check_defaults.
pt_shell> check_timing
Information: Checking 'no_clock'.
Warning: There are 4 register clock pins with no clock.
Information: Checking 'no_input_delay'.
Information: Checking 'unconstrained_endpoints'.
Warning: There are 10 endpoints which are not constrained for maximum delay.
Information: Checking 'generic'.
Information: Checking 'latch_fanout'.
Warning: There are 2 level-sensitive latches which fanout to themselves.
Information: There are 2 level-sensitive latches which fanout to latches
of the same clock.
Information: Checking 'loops'.
Warning: There are 6 timing loops in the design.
Information: Checking 'generated_clocks'.
The following example adds the clock_crossing check to the list of
checks in timing_check_defaults.
pt_shell> check_timing -include {clock_crossing}
Information: Checking 'no_clock'.
Warning: There are 4 register clock pins with no clock.
Information: Checking 'no_input_delay'.
Information: Checking 'unconstrained_endpoints'.
Warning: There are 10 endpoints which are not constrained for maximum delay.
Information: Checking 'generic'.
Information: Checking 'latch_fanout'.
Warning: There are 2 level-sensitive latches which fanout to themselves.
Information: There are 2 level-sensitive latches which fanout to latches
of the same clock.
Information: Checking 'loops'.
Warning: There are 6 timing loops in the design.
Information: Checking 'generated_clocks'.
Information: Checking 'clock_crossing'.
Information: Checking 'pll_configuration'.
The following example adds the clock_crossing check to the list of
checks in timing_check_defaults and removes the loops check from the
same list.
pt_shell> check_timing -include {clock_crossing} -exclude {loops}
Information: Checking 'no_clock'.
Warning: There are 4 register clock pins with no clock.
Information: Checking 'no_input_delay'.
Information: Checking 'unconstrained_endpoints'.
Warning: There are 10 endpoints which are not constrained for maximum delay.
Information: Checking 'generic'.
Information: Checking 'latch_fanout'.
Warning: There are 2 level-sensitive latches which fanout to themselves.
Information: There are 2 level-sensitive latches which fanout to latches
of the same clock.
Information: Checking 'generated_clocks'.
Information: Checking 'clock_crossing'.
The following example removes the retain option from the list of checks
in timing_check_defaults. Assuming that this check is not included in
timing_check_defaults, there is nothing to remove. The output in this
example is the same as running the command without the -exclude option.
pt_shell> check_timing -exclude {retain}
Information: Checking 'no_clock'.
Warning: There are 4 register clock pins with no clock.
Information: Checking 'no_input_delay'.
Information: Checking 'unconstrained_endpoints'.
Warning: There are 10 endpoints which are not constrained for maximum delay.
Information: Checking 'generic'.
Information: Checking 'latch_fanout'.
Warning: There are 2 level-sensitive latches which fanout to themselves.
Information: There are 2 level-sensitive latches which fanout to latches
of the same clock.
Information: Checking 'loops'.
Warning: There are 6 timing loops in the design.
Information: Checking 'generated_clocks'.
The following example checks only latch fanout and shows detailed
information.
pt_shell> check_timing -verbose -override_defaults {latch_fanout}
Warning: There are 2 level-sensitive latches which fanout to themselves.
Latch data pin
------------------------------------------------------------
l3/D
l4/D
Information: There are 2 level-sensitive latches which fanout to latches
of the same clock.
From Pin To Pin Clock Level
--------------------------------------------------------------------------------
l1/G l2/D C1 positive
l1/G l3/D C1 positive
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