ECO flow with examples

http://tech.tdzire.com/timing-eco-flow-with-examples/


At the early stage of the design,
1. See whether the skew of the launch and the capture clocks are balanced.
If launch clock is having more latency, the data will come late to the capture flop,
and thus result in setup violations.


For setup violations:
 - increase the capture clock latency
 - decrease the launch clock latency with set_anootated_delay command
and see whether it is not resulting in any additional violations and viceversa
 for HOLD violations.


At matured stage of the design:
1. Try not to touch clock tree.
2. Decrease data path delay.
 - size up, change to lower vt,


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If there are a lot of violations and power is not critical:
report_timing -slack_lesser_than 0 -max_paths 200000 -nworst 100 -delay max > max_paths.rpt
DMSA setup can check ECO across modes and corners in one shot.


During final stage, do VT swap only as it will not disturb DRC.