Clock Distribution Techniques

https://www.slideshare.net/KaushalPanchal1/clock-distribution-41503463

https://www.slideshare.net/vlsisyst/vlsi-academy-clock-tree-synthesis?next_slideshow=1

Clocking:

The clock distribution network is the metal and buffer network that distribute clock to all clocked segment.

A clock generator is a circuit that produces a timing signal for use in synchronizing a system's operation.

Primary challenges in clock distribution:

1. Need to support higher clock frequency based on the strong correlation between frequency and chip performance.
2. Process technology scaling allows higher level of integration and larger die size leading to higher clock loading and larger distances the clock network need to traverse.

Main factors effect clock distribution:

1. Skew:
1.  It is a phenomenon in synchronous circuits in which the clock signal arrives at different components at different times.
2. Clock skew is due to the unbalanced of the data.
3. Strategies to remove skew:
1. Locate all clock inputs close together; but it is difficult to implement in a large circuit.
2. Drive them from the same source & balance the delays.
2. Jitter: It is the cycle time variation of consecutive clock periods.
3. Power dissipation:
1. Clock node consumes more power than any other nodes on the chip.
2. Clock tree dissipate 40% of total power.

Clock Distribution Topologies:

1. Unconstrained Tree:
1. No constraints imposed on buffers and wires.
2. Used mostly by automatic tools in automatic synthesis flows.
3. Can be used for small blocks within large design.

2. Balanced Tree:
1. The length of interconnects is identical from the source node to the 2 destination nodes.
2. The primary delay difference among the clock signal paths is due to the variations of process parameters affection
1. Interconnect impedance
2. Characteristics of buffer
3. This structure is difficult to implement in practice due to:
1. Routing constraints
2. Different fan-out requirements.

3. Central Spine:
1. It is a specific implementation of a binary tree.
2. The clock can be transported in a balanced fashion across one dimension of the die with low structural skew.

4. Spines with matched branches:
1. An extension of the central spine structure can be realized by replacing the unconstrained end-of-distribution branches with delay matched routes.
2. The longest branch determines the delay from the output of the central spine to the end loads.

5. Grid:
1. The clock grid resembles a mesh with fully connected clock tracks in both dimensions and grid drivers located on all 4 sides.
2. Usually a custom implementation, simple to build
3. Insensitive to load changes
4. Dissipate more power.

6. Hybrid distribution:
1. It is the combination of all the topologies.
2. Common configurations are spine-grid distribution or tree-grid distribution
3. It employs a multilevel H-tree driving a common grid.