Clock push or pull techniques

Identifying common cell in the multi branch flops (next stage):

report_transitive_fanin -from FF1/clk

see from which cell it is diverging and do insert_buffer at the cell, to fix on all the cells at the same time.


Good clock tree:
Diverging of the clock path should be close to the flops otherwise

i) No of cells are more => results high dynamic power
ii) Common path should be as long as possible (CRP should be high) otherwise pvt, Rc corner variaions and skew is more => high uncertainity values

Because of bad clock tree, worst hold failures may happen at min, low voltage compared to min, high voltage corners.