Let us assume,
FF1 - launch flop (rising edge)
FF2 - capture flop (rising edge)
Always setup and hold checks are w.r.t to capture flop.
Setup Timing check:
Data (D1) is launched at rising edge1 will be captured at rising edge2 of capture flop.
Here, it should satisfy setup time of FF2 to capture the launched data successfully. Hence, setup timing check is always checked at next clock cycle.
Min Clock period (T) > Tcq1+ Tcomb+ Tsu2
Hold Timing Check:
Data (D1) should be stable for minimum Thold time (Tcq1,min + Tcomb1,min > Thold) so that it doesn't overwrite the data (D2) that is going to be captured by FF2.
Where this check needs to applied:
i) Launched data at edge1 should be captured by capture clk @edge2.
ii) In other words, what ever data launched @edge1 should not be captured @edge1 of capture clock. So this needs to be tested in the same clock edges.That's why it is called "Zero cycle check".
Mathematically the data should change only after (Tcq,min + Tcomb,min) only. Then only it will not overwrite the capture flop data.
This has to be checked at launch edge (i.e. edge1) of FF1. So, hold timing check is zero cycle check and it doesn't depend on time period of clock (independent of frequency).
Tcq1,min + Tcomb1, min > Thold
The intention is for the data from the launch FF to be captured by the capture FF in the next clock cycle. If the data is captured in the same clock cycle, the intended data in the capture FF (from the prev clock cycle) is overwritten. The hold time check is to ensure that the intended data in the capture FF is not overwritten.
Hold timing check ensures that
Launch FF output value that is changing doesn't pass through to a capture FF and
overwrite its output before the FF has had a chance to capture its original value
So, data being latched should be held stable for a specified amount of time after the
active edge of the clock ==> This min amount of time is referred to as Hold time of FF.
The hold check is carried out on each active edge of the clock of the capture FF.
setup timing check -> data launched by FF1 needs to be captured @FF2
hold timing check -> to make sure that correct data is not overwritten by subsequent data @FF2
After manufacturing,
i) Still setup violation is there, operate chip at lower frequency
ii) But if hold violation is there, design inoperable at any frequency (as it checks minimum delays). So make sure to resolve all hold timing violations.
FF1 - launch flop (rising edge)
FF2 - capture flop (rising edge)
Always setup and hold checks are w.r.t to capture flop.
Setup Timing check:
Data (D1) is launched at rising edge1 will be captured at rising edge2 of capture flop.
Here, it should satisfy setup time of FF2 to capture the launched data successfully. Hence, setup timing check is always checked at next clock cycle.
Min Clock period (T) > Tcq1+ Tcomb+ Tsu2
Hold Timing Check:
Data (D1) should be stable for minimum Thold time (Tcq1,min + Tcomb1,min > Thold) so that it doesn't overwrite the data (D2) that is going to be captured by FF2.
Where this check needs to applied:
i) Launched data at edge1 should be captured by capture clk @edge2.
ii) In other words, what ever data launched @edge1 should not be captured @edge1 of capture clock. So this needs to be tested in the same clock edges.That's why it is called "Zero cycle check".
Mathematically the data should change only after (Tcq,min + Tcomb,min) only. Then only it will not overwrite the capture flop data.
This has to be checked at launch edge (i.e. edge1) of FF1. So, hold timing check is zero cycle check and it doesn't depend on time period of clock (independent of frequency).
Tcq1,min + Tcomb1, min > Thold
The intention is for the data from the launch FF to be captured by the capture FF in the next clock cycle. If the data is captured in the same clock cycle, the intended data in the capture FF (from the prev clock cycle) is overwritten. The hold time check is to ensure that the intended data in the capture FF is not overwritten.
Hold timing check ensures that
Launch FF output value that is changing doesn't pass through to a capture FF and
overwrite its output before the FF has had a chance to capture its original value
So, data being latched should be held stable for a specified amount of time after the
active edge of the clock ==> This min amount of time is referred to as Hold time of FF.
The hold check is carried out on each active edge of the clock of the capture FF.
setup timing check -> data launched by FF1 needs to be captured @FF2
hold timing check -> to make sure that correct data is not overwritten by subsequent data @FF2
After manufacturing,
i) Still setup violation is there, operate chip at lower frequency
ii) But if hold violation is there, design inoperable at any frequency (as it checks minimum delays). So make sure to resolve all hold timing violations.
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